Inproceedings,
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features.
Y. Ryu, Y. Kwon, J. Lee, S. Ahn, J. Park, K. Lee, Y. Choi, H. Cho, J. Kim, J. Lee, H. Lee, S. Song, J. Ryu, Y. Yun, U. Shin, D. Cho, J. Park, J. Jeong, S. Lee, K. Lim, T. Kim, K. Kim, Y. Cha, I. Lee, T. Byun, H. Yoo, Y. Song, M. Lee, S. Cho, S. Kim, J. Choi, H. Kim, S. Kim, J. Youn, M. Kim, K. Sohn, S. Hwang, and J. Lee.VLSI Technology and Circuits, page 130-131. IEEE, (2022)
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- conf/vlsit/RyuKLAPLCCK0LSR22
- entry type
- inproceedings
- booktitle
- VLSI Technology and Circuits
- year
- 2022
- pages
- 130-131
- publisher
- IEEE
- crossref
- conf/vlsit/2022
- ee
- https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830391
- isbn
- 978-1-6654-9772-5
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- http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#RyuKLAPLCCK0LSR22
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%1 conf/vlsit/RyuKLAPLCCK0LSR22
%A Ryu, Yesin
%A Kwon, Young-Cheon
%A Lee, Jae Hoon
%A Ahn, Sung-Gi
%A Park, Jaewon
%A Lee, Kijun
%A Choi, Yu Ho
%A Cho, Han-Won
%A Kim, Jae San
%A Lee, Jungyu
%A Lee, Haesuk
%A Song, Seung Ho
%A Ryu, Je-Min
%A Yun, Yeong Ho
%A Shin, Useung
%A Cho, Dajung
%A Park, Jeong Hoan
%A Jeong, Jae-Seung
%A Lee, Suk Han
%A Lim, Kyounghwan
%A Kim, Tae-Sung
%A Kim, Kyungmin
%A Cha, Yu Jin
%A Lee, Ik Joo
%A Byun, Tae Kyu
%A Yoo, Han Sik
%A Song, Yeong Geol
%A Lee, Myung-Kyu
%A Cho, Sunghye
%A Kim, Sung-Rae
%A Choi, Ji-Min
%A Kim, Hyoungmin
%A Kim, Soo Young
%A Youn, Jaeyoun
%A Kim, Myeong-O.
%A Sohn, Kyomin
%A Hwang, SangJoon
%A Lee, JooYoung
%B VLSI Technology and Circuits
%D 2022
%I IEEE
%K dblp
%P 130-131
%T A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features.
%U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#RyuKLAPLCCK0LSR22
%@ 978-1-6654-9772-5
@inproceedings{conf/vlsit/RyuKLAPLCCK0LSR22,
added-at = {2024-04-18T00:00:00.000+0200},
author = {Ryu, Yesin and Kwon, Young-Cheon and Lee, Jae Hoon and Ahn, Sung-Gi and Park, Jaewon and Lee, Kijun and Choi, Yu Ho and Cho, Han-Won and Kim, Jae San and Lee, Jungyu and Lee, Haesuk and Song, Seung Ho and Ryu, Je-Min and Yun, Yeong Ho and Shin, Useung and Cho, Dajung and Park, Jeong Hoan and Jeong, Jae-Seung and Lee, Suk Han and Lim, Kyounghwan and Kim, Tae-Sung and Kim, Kyungmin and Cha, Yu Jin and Lee, Ik Joo and Byun, Tae Kyu and Yoo, Han Sik and Song, Yeong Geol and Lee, Myung-Kyu and Cho, Sunghye and Kim, Sung-Rae and Choi, Ji-Min and Kim, Hyoungmin and Kim, Soo Young and Youn, Jaeyoun and Kim, Myeong-O. and Sohn, Kyomin and Hwang, SangJoon and Lee, JooYoung},
biburl = {https://www.bibsonomy.org/bibtex/2f05a603e0312958c649409657cf2dcff/dblp},
booktitle = {VLSI Technology and Circuits},
crossref = {conf/vlsit/2022},
ee = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830391},
interhash = {c9a4702114075d40b19270d64656d617},
intrahash = {f05a603e0312958c649409657cf2dcff},
isbn = {978-1-6654-9772-5},
keywords = {dblp},
pages = {130-131},
publisher = {IEEE},
timestamp = {2024-04-22T07:45:38.000+0200},
title = {A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features.},
url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#RyuKLAPLCCK0LSR22},
year = 2022
}