%0 Conference Paper %1 conf/esscirc/HaqueLHKJWPHD14 %A Haque, Yusuf %A Lewis, Donald E. %A Hales, Rex %A Kier, Ryan J. %A Johancsik, Tracy %A Watkins, Paul T. %A Picken, William %A Harper, Marcellus %A Dujari, Shyam %B ESSCIRC %D 2014 %I IEEE %K dblp %P 59-62 %T Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration. %U http://dblp.uni-trier.de/db/conf/esscirc/esscirc2014.html#HaqueLHKJWPHD14 %@ 978-1-4799-5694-4

@inproceedings{conf/esscirc/HaqueLHKJWPHD14, added-at = {2017-05-26T00:00:00.000+0200}, author = {Haque, Yusuf and Lewis, Donald E. and Hales, Rex and Kier, Ryan J. and Johancsik, Tracy and Watkins, Paul T. and Picken, William and Harper, Marcellus and Dujari, Shyam}, biburl = {https://www.bibsonomy.org/bibtex/21291be0e7123e32fbdc86f49ee4d8db7/dblp}, booktitle = {ESSCIRC}, crossref = {conf/esscirc/2014}, ee = {https://doi.org/10.1109/ESSCIRC.2014.6942021}, interhash = {ca802df00e525f4e00b39b3b61bd8774}, intrahash = {1291be0e7123e32fbdc86f49ee4d8db7}, isbn = {978-1-4799-5694-4}, keywords = {dblp}, pages = {59-62}, publisher = {IEEE}, timestamp = {2019-10-17T20:56:45.000+0200}, title = {Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration.}, url = {http://dblp.uni-trier.de/db/conf/esscirc/esscirc2014.html#HaqueLHKJWPHD14}, year = 2014 }