%0 Journal Article %1 1 %A Jia, Huizhu %A Zhang, Peng %A Xie, D %A Gao, Wen %D 2006 %J Consumer Electronics, IEEE Transactions on %K master paper %N 4 %P 1447-1453 %T An AVS HDTV video decoder architecture employing efficient HW/SW partitioning %U http://dx.doi.org/10.1109/TCE.2006.273169 %V 52 %X In this paper, we propose an optimized real-time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder. The decoder has been implemented in a single SoC with HW/SW partitioning. AVS algorithms and complexity are first analyzed. Based on the analysis, a hardware implementation of the MB level 7-stage pipeline is selected. The software tasks are realized with a 32-bit RISC processor. We further propose the optimization of interface and RISC processor based on the proposed architecture. The AVS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip AVS HDTV real-time decoder. At 148.5 MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 frames/s or 1080i@60 fields/s) bit-streams. Finally, the decoder has been fully tested on a prototyping board

@article{1, abstract = {In this paper, we propose an optimized real-time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder. The decoder has been implemented in a single SoC with HW/SW partitioning. AVS algorithms and complexity are first analyzed. Based on the analysis, a hardware implementation of the MB level 7-stage pipeline is selected. The software tasks are realized with a 32-bit RISC processor. We further propose the optimization of interface and RISC processor based on the proposed architecture. The AVS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip AVS HDTV real-time decoder. At 148.5 MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 frames/s or 1080i@60 fields/s) bit-streams. Finally, the decoder has been fully tested on a prototyping board }, added-at = {2008-11-27T06:53:45.000+0100}, author = {Jia, Huizhu and Zhang, Peng and Xie, D and Gao, Wen}, biburl = {https://www.bibsonomy.org/bibtex/21ca675c255f1a2f9d1402e96eaeb73e1/rnmichelle}, description = {These papers are searched for my master paper writing.}, interhash = {1cac646590b7e04d8f0c51ea0485aa6a}, intrahash = {1ca675c255f1a2f9d1402e96eaeb73e1}, journal = {Consumer Electronics, IEEE Transactions on}, keywords = {master paper}, month = {Nov.}, note = {for my master paper_1}, number = 4, pages = {1447-1453}, timestamp = {2008-12-09T16:28:12.000+0100}, title = {An AVS HDTV video decoder architecture employing efficient HW/SW partitioning }, url = {http://dx.doi.org/10.1109/TCE.2006.273169 }, volume = 52, year = 2006 }