%0 Journal Article %1 journals/iet-cds/SahaBBD14 %A Saha, Prabir %A Banerjee, Arindam %A Bhattacharyya, Partha %A Dandapat, Anup %D 2014 %J IET Circuits Devices Syst. %K dblp %N 1 %P 27-37 %T Improved matrix multiplier design for high-speed digital signal processing applications. %U http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds8.html#SahaBBD14 %V 8

@article{journals/iet-cds/SahaBBD14, added-at = {2023-09-30T00:00:00.000+0200}, author = {Saha, Prabir and Banerjee, Arindam and Bhattacharyya, Partha and Dandapat, Anup}, biburl = {https://www.bibsonomy.org/bibtex/2891f32524586453f985311e2216b1cd3/dblp}, ee = {https://doi.org/10.1049/iet-cds.2013.0117}, interhash = {cb8bf5614940c8d0cb33d0ccd01a95ce}, intrahash = {891f32524586453f985311e2216b1cd3}, journal = {IET Circuits Devices Syst.}, keywords = {dblp}, number = 1, pages = {27-37}, timestamp = {2024-04-08T16:07:19.000+0200}, title = {Improved matrix multiplier design for high-speed digital signal processing applications.}, url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds8.html#SahaBBD14}, volume = 8, year = 2014 }