%0 Conference Paper %1 conf/vlsit/JungLKLKOL23 %A Jung, Jaehong %A Lee, Kyungmin %A Kong, Gunwoo %A Lim, Baekmin %A Kim, Seungjin %A Oh, Seunghyun %A Lee, Jongwoo %B VLSI Technology and Circuits %D 2023 %I IEEE %K dblp %P 1-2 %T A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#JungLKLKOL23 %@ 978-4-86348-806-9

@inproceedings{conf/vlsit/JungLKLKOL23, added-at = {2023-09-30T00:00:00.000+0200}, author = {Jung, Jaehong and Lee, Kyungmin and Kong, Gunwoo and Lim, Baekmin and Kim, Seungjin and Oh, Seunghyun and Lee, Jongwoo}, biburl = {https://www.bibsonomy.org/bibtex/2d72fd4967f3451c50c3a392a00c97f3a/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2023}, ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185300}, interhash = {cbda948c880dea94c754402da3dac9b8}, intrahash = {d72fd4967f3451c50c3a392a00c97f3a}, isbn = {978-4-86348-806-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:01.000+0200}, title = {A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#JungLKLKOL23}, year = 2023 }