%0 Journal Article %1 journals/tcasI/WangYHDTWH21 %A Wang, Zhixuan %A Ye, Le %A Huang, Qianqian %A Du, Kaixuan %A Tan, Zhichao %A Wang, Yangyuan %A Huang, Ru %D 2021 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 3 %P 1160-1170 %T Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process. %U http://dblp.uni-trier.de/db/journals/tcasI/tcasI68.html#WangYHDTWH21 %V 68

@article{journals/tcasI/WangYHDTWH21, added-at = {2024-06-03T00:00:00.000+0200}, author = {Wang, Zhixuan and Ye, Le and Huang, Qianqian and Du, Kaixuan and Tan, Zhichao and Wang, Yangyuan and Huang, Ru}, biburl = {https://www.bibsonomy.org/bibtex/27162f8d0d32b41d1dc434e5706a357c0/dblp}, ee = {https://www.wikidata.org/entity/Q114085028}, interhash = {cd5b15c6597a5ca4041000a4d5af4138}, intrahash = {7162f8d0d32b41d1dc434e5706a357c0}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 3, pages = {1160-1170}, timestamp = {2024-06-10T07:03:10.000+0200}, title = {Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process.}, url = {http://dblp.uni-trier.de/db/journals/tcasI/tcasI68.html#WangYHDTWH21}, volume = 68, year = 2021 }