%0 Conference Paper %1 conf/icassp/OkadaESYSI84 %A Okada, K. %A Ehara, T. %A Suzuki, H. %A Yanagida, K. %A Saito, K. %A Ichiura, N. %B ICASSP %D 1984 %I IEEE %K dblp %P 378-381 %T A digital signal processor module architecture and its implementation using VLSIs. %U http://dblp.uni-trier.de/db/conf/icassp/icassp1984.html#OkadaESYSI84

@inproceedings{conf/icassp/OkadaESYSI84, added-at = {2017-05-19T00:00:00.000+0200}, author = {Okada, K. and Ehara, T. and Suzuki, H. and Yanagida, K. and Saito, K. and Ichiura, N.}, biburl = {https://www.bibsonomy.org/bibtex/2b83e105f7183f24e2683281151787ee4/dblp}, booktitle = {ICASSP}, crossref = {conf/icassp/1984}, ee = {https://doi.org/10.1109/ICASSP.1984.1172728}, interhash = {cd72154daa459da307328d958ba4ba03}, intrahash = {b83e105f7183f24e2683281151787ee4}, keywords = {dblp}, pages = {378-381}, publisher = {IEEE}, timestamp = {2019-10-17T17:15:09.000+0200}, title = {A digital signal processor module architecture and its implementation using VLSIs.}, url = {http://dblp.uni-trier.de/db/conf/icassp/icassp1984.html#OkadaESYSI84}, year = 1984 }