%0 Journal Article %1 journals/jssc/FujisawaHTSFSU03 %A Fujisawa, Toshio %A Hasegawa, Jun %A Tsuchie, Koji %A Shiozawa, Tatsuo %A Fujita, Tetsuya %A Saito, Toshitada %A Unekawa, Yasuo %D 2003 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 2001-2009 %T A single-chip 802.11a MAC/PHY with a 32-b RISC processor. %U http://dblp.uni-trier.de/db/journals/jssc/jssc38.html#FujisawaHTSFSU03 %V 38

@article{journals/jssc/FujisawaHTSFSU03, added-at = {2022-04-20T00:00:00.000+0200}, author = {Fujisawa, Toshio and Hasegawa, Jun and Tsuchie, Koji and Shiozawa, Tatsuo and Fujita, Tetsuya and Saito, Toshitada and Unekawa, Yasuo}, biburl = {https://www.bibsonomy.org/bibtex/287f9c63ce3be2189c6b89d3193a96395/dblp}, ee = {https://doi.org/10.1109/JSSC.2003.818135}, interhash = {cfb938b7cda773a644aa6d46cea9c09a}, intrahash = {87f9c63ce3be2189c6b89d3193a96395}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {2001-2009}, timestamp = {2024-04-08T10:42:26.000+0200}, title = {A single-chip 802.11a MAC/PHY with a 32-b RISC processor.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc38.html#FujisawaHTSFSU03}, volume = 38, year = 2003 }