%0 Conference Paper %1 conf/vlsid/Chakraborty05 %A Chakraborty, Avik %B VLSI Design %D 2005 %I IEEE Computer Society %K dblp %P 249-254 %T Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#Chakraborty05 %@ 0-7695-2264-5

@inproceedings{conf/vlsid/Chakraborty05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Chakraborty, Avik}, biburl = {https://www.bibsonomy.org/bibtex/2a384080fe84981ff2fba981021882565/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2005}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.158}, interhash = {d3e2ab9a8dddee8f215a7c18038350b7}, intrahash = {a384080fe84981ff2fba981021882565}, isbn = {0-7695-2264-5}, keywords = {dblp}, pages = {249-254}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:41.000+0200}, title = {Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#Chakraborty05}, year = 2005 }