%0 Conference Paper %1 conf/fskd/ChenZ14a %A Chen, Jianli %A Zhu, Wenxing %B FSKD %D 2014 %I IEEE %K dblp %P 881-885 %T A scaled LSE wirelength model for VLSI global placement. %U http://dblp.uni-trier.de/db/conf/fskd/fskd2014.html#ChenZ14a %@ 978-1-4799-5147-5

@inproceedings{conf/fskd/ChenZ14a, added-at = {2014-12-21T00:00:00.000+0100}, author = {Chen, Jianli and Zhu, Wenxing}, biburl = {https://www.bibsonomy.org/bibtex/2fbac4888cdd2e9862bc1af3783a63ce6/dblp}, booktitle = {FSKD}, crossref = {conf/fskd/2014}, ee = {http://dx.doi.org/10.1109/FSKD.2014.6980955}, interhash = {d47716b644066bf88d3c9d263b49c839}, intrahash = {fbac4888cdd2e9862bc1af3783a63ce6}, isbn = {978-1-4799-5147-5}, keywords = {dblp}, pages = {881-885}, publisher = {IEEE}, timestamp = {2015-06-19T00:36:26.000+0200}, title = {A scaled LSE wirelength model for VLSI global placement.}, url = {http://dblp.uni-trier.de/db/conf/fskd/fskd2014.html#ChenZ14a}, year = 2014 }