%0 Journal Article %1 journals/tcad/LiaoTYTSZZL16 %A Liao, Changhai %A Tao, Jun %A Yu, Handi %A Tang, Zhangwen %A Su, Yangfeng %A Zhou, Dian %A Zeng, Xuan %A Li, Xin %D 2016 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 12 %P 2148-2152 %T Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. %U http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#LiaoTYTSZZL16 %V 35

@article{journals/tcad/LiaoTYTSZZL16, added-at = {2020-09-24T00:00:00.000+0200}, author = {Liao, Changhai and Tao, Jun and Yu, Handi and Tang, Zhangwen and Su, Yangfeng and Zhou, Dian and Zeng, Xuan and Li, Xin}, biburl = {https://www.bibsonomy.org/bibtex/205819ae419c86f99601b2da48356b826/dblp}, ee = {https://doi.org/10.1109/TCAD.2016.2543021}, interhash = {da70f300bcb722b08cca7c45907759c0}, intrahash = {05819ae419c86f99601b2da48356b826}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 12, pages = {2148-2152}, timestamp = {2020-09-25T11:46:56.000+0200}, title = {Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#LiaoTYTSZZL16}, volume = 35, year = 2016 }