%0 Journal Article %1 journals/tvlsi/LernerYT19 %A Lerner, Scott %A Yilmaz, Isikcan %A Taskin, Baris %D 2019 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 700-710 %T Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#LernerYT19 %V 27

@article{journals/tvlsi/LernerYT19, added-at = {2020-03-11T00:00:00.000+0100}, author = {Lerner, Scott and Yilmaz, Isikcan and Taskin, Baris}, biburl = {https://www.bibsonomy.org/bibtex/2da2379476f0a8e66a93983a61f2fe5d9/dblp}, ee = {https://doi.org/10.1109/TVLSI.2018.2878664}, interhash = {db0288d5871c64d4068a7e1202437cb7}, intrahash = {da2379476f0a8e66a93983a61f2fe5d9}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {700-710}, timestamp = {2020-03-12T11:45:17.000+0100}, title = {Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#LernerYT19}, volume = 27, year = 2019 }