%0 Journal Article %1 journals/cee/KarthikeyanK17 %A Karthikeyan, A. %A Kumar, P. Senthil %D 2017 %J Comput. Electr. Eng. %K dblp %P 39-50 %T Randomly prioritized buffer-less routing architecture for 3D Network on Chip. %U http://dblp.uni-trier.de/db/journals/cee/cee59.html#KarthikeyanK17 %V 59

@article{journals/cee/KarthikeyanK17, added-at = {2022-04-27T00:00:00.000+0200}, author = {Karthikeyan, A. and Kumar, P. Senthil}, biburl = {https://www.bibsonomy.org/bibtex/27a8550dddd2c8d75663e7b2fb48fe8ea/dblp}, ee = {https://doi.org/10.1016/j.compeleceng.2017.03.006}, interhash = {e479fd035fe4624e567d6a944acc8a18}, intrahash = {7a8550dddd2c8d75663e7b2fb48fe8ea}, journal = {Comput. Electr. Eng.}, keywords = {dblp}, pages = {39-50}, timestamp = {2024-04-08T18:53:51.000+0200}, title = {Randomly prioritized buffer-less routing architecture for 3D Network on Chip.}, url = {http://dblp.uni-trier.de/db/journals/cee/cee59.html#KarthikeyanK17}, volume = 59, year = 2017 }