%0 Conference Paper %1 conf/fpl/CapalijaA14 %A Capalija, Davor %A Abdelrahman, Tarek S. %B FPL %D 2014 %I IEEE %K dblp %P 1-8 %T Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#CapalijaA14

@inproceedings{conf/fpl/CapalijaA14, added-at = {2017-05-21T00:00:00.000+0200}, author = {Capalija, Davor and Abdelrahman, Tarek S.}, biburl = {https://www.bibsonomy.org/bibtex/2f7437dcc55091b5a63dc74e3af0224f3/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2014}, ee = {https://doi.org/10.1109/FPL.2014.6927456}, interhash = {e6c46e48777cdbbd22a7d05a4ffba4e7}, intrahash = {f7437dcc55091b5a63dc74e3af0224f3}, keywords = {dblp}, pages = {1-8}, publisher = {IEEE}, timestamp = {2019-10-17T19:13:37.000+0200}, title = {Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#CapalijaA14}, year = 2014 }