%0 Conference Paper %1 conf/vlsid/BalasubramanianNFG06 %A Balasubramanian, Suresh %A Natarajan, Narayanan %A Franza, Olivier %A Gianos, Chris %B VLSI Design %D 2006 %I IEEE Computer Society %K dblp %P 781-785 %T Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2006.html#BalasubramanianNFG06 %@ 0-7695-2502-4

@inproceedings{conf/vlsid/BalasubramanianNFG06, added-at = {2023-03-24T00:00:00.000+0100}, author = {Balasubramanian, Suresh and Natarajan, Narayanan and Franza, Olivier and Gianos, Chris}, biburl = {https://www.bibsonomy.org/bibtex/2c2d3f62cec992fa4abca3668fbb4f3dc/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2006}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.71}, interhash = {e6f923e0508af7e0be34e1c9d8b29163}, intrahash = {c2d3f62cec992fa4abca3668fbb4f3dc}, isbn = {0-7695-2502-4}, keywords = {dblp}, pages = {781-785}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:17:52.000+0200}, title = {Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2006.html#BalasubramanianNFG06}, year = 2006 }