%0 Conference Paper %1 conf/asicon/PangJWLYN19 %A Pang, Yalong %A Jiang, Shuai %A yuan Wang, Lu %A Liu, Weiwei %A yang Yu, Ji %A Niu, Yuehua %B ASICON %D 2019 %I IEEE %K dblp %P 1-4 %T A Lightweight Slave-Module Interface Core to Implement IEEE 1149.5 MTM-Bus Based on FPGA. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2019.html#PangJWLYN19 %@ 978-1-7281-0735-6

@inproceedings{conf/asicon/PangJWLYN19, added-at = {2020-02-12T00:00:00.000+0100}, author = {Pang, Yalong and Jiang, Shuai and yuan Wang, Lu and Liu, Weiwei and yang Yu, Ji and Niu, Yuehua}, biburl = {https://www.bibsonomy.org/bibtex/27dc8c410fea81c5a801afbc0708971af/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2019}, ee = {https://doi.org/10.1109/ASICON47005.2019.8983524}, interhash = {e849e01204fd797cdd7d1ae3b1abf90c}, intrahash = {7dc8c410fea81c5a801afbc0708971af}, isbn = {978-1-7281-0735-6}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2020-02-13T12:22:20.000+0100}, title = {A Lightweight Slave-Module Interface Core to Implement IEEE 1149.5 MTM-Bus Based on FPGA.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2019.html#PangJWLYN19}, year = 2019 }