%0 Journal Article %1 journals/tvlsi/FuHSMLY23 %A Fu, Yushen %A Huang, Chengyu %A Sun, Limeng %A Meng, Weiguang %A Li, Xueqing %A Yang, Huazhong %D 2023 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 2 %P 199-209 %T A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi31.html#FuHSMLY23 %V 31

@article{journals/tvlsi/FuHSMLY23, added-at = {2024-09-19T00:00:00.000+0200}, author = {Fu, Yushen and Huang, Chengyu and Sun, Limeng and Meng, Weiguang and Li, Xueqing and Yang, Huazhong}, biburl = {https://www.bibsonomy.org/bibtex/2044a836e737a8ecf516e5a6507ee524a/dblp}, ee = {https://doi.org/10.1109/TVLSI.2022.3232516}, interhash = {e8a830bdf7c17e085c47dee0717eaef1}, intrahash = {044a836e737a8ecf516e5a6507ee524a}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, month = {February}, number = 2, pages = {199-209}, timestamp = {2024-09-23T07:03:55.000+0200}, title = {A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi31.html#FuHSMLY23}, volume = 31, year = 2023 }