Article,
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic.
S. Raveendran, P. Edavoor, N. Balachandra, and M. Vasantha.IEEE Access, (2021)
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- journals/access/RaveendranEBV21
- entry type
- article
- year
- 2021
- journal
- IEEE Access
- pages
- 108119-108130
- volume
- 9
- ee
- https://doi.org/10.1109/ACCESS.2021.3100892
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- http://dblp.uni-trier.de/db/journals/access/access9.html#RaveendranEBV21
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%1 journals/access/RaveendranEBV21
%A Raveendran, Sithara
%A Edavoor, Pranose J.
%A Balachandra, Nithin Kumar Yernad
%A Vasantha, M. H.
%D 2021
%J IEEE Access
%K dblp
%P 108119-108130
%T Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic.
%U http://dblp.uni-trier.de/db/journals/access/access9.html#RaveendranEBV21
%V 9
@article{journals/access/RaveendranEBV21,
added-at = {2021-08-12T00:00:00.000+0200},
author = {Raveendran, Sithara and Edavoor, Pranose J. and Balachandra, Nithin Kumar Yernad and Vasantha, M. H.},
biburl = {https://www.bibsonomy.org/bibtex/2194a5915cf2b7d105408a8546ba00fd7/dblp},
ee = {https://doi.org/10.1109/ACCESS.2021.3100892},
interhash = {e8eb711167edf8a795bf33d56653b625},
intrahash = {194a5915cf2b7d105408a8546ba00fd7},
journal = {IEEE Access},
keywords = {dblp},
pages = {108119-108130},
timestamp = {2024-04-08T14:04:31.000+0200},
title = {Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic.},
url = {http://dblp.uni-trier.de/db/journals/access/access9.html#RaveendranEBV21},
volume = 9,
year = 2021
}