%0 Journal Article %1 journals/ijcta/ZhangLDHLX16 %A Zhang, Yongqiang %A Lv, Hongjun %A Du, Huakun %A Huang, Cheng %A Liu, Shuai %A Xie, Guangjun %D 2016 %J Int. J. Circuit Theory Appl. %K dblp %N 7 %P 1351-1366 %T Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates. %U http://dblp.uni-trier.de/db/journals/ijcta/ijcta44.html#ZhangLDHLX16 %V 44

@article{journals/ijcta/ZhangLDHLX16, added-at = {2021-08-27T00:00:00.000+0200}, author = {Zhang, Yongqiang and Lv, Hongjun and Du, Huakun and Huang, Cheng and Liu, Shuai and Xie, Guangjun}, biburl = {https://www.bibsonomy.org/bibtex/2f33e67d1848debba546300e491f44e6e/dblp}, ee = {https://doi.org/10.1002/cta.2163}, interhash = {ea5f7e8aeb4dfff8deb6d6b28256cc42}, intrahash = {f33e67d1848debba546300e491f44e6e}, journal = {Int. J. Circuit Theory Appl.}, keywords = {dblp}, number = 7, pages = {1351-1366}, timestamp = {2024-04-08T20:20:53.000+0200}, title = {Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates.}, url = {http://dblp.uni-trier.de/db/journals/ijcta/ijcta44.html#ZhangLDHLX16}, volume = 44, year = 2016 }