%0 Journal Article %1 journals/tcad/YangWHTC18 %A Yang, Shaofu %A Wen, Zhi-Yuan %A Huang, Shi-Yu %A Tsai, Kun-Han %A Cheng, Wu-Tung %D 2018 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 10 %P 2087-2097 %T Circuit and Methodology for Testing Small Delay Faults in the Clock Network. %U http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#YangWHTC18 %V 37

@article{journals/tcad/YangWHTC18, added-at = {2020-09-24T00:00:00.000+0200}, author = {Yang, Shaofu and Wen, Zhi-Yuan and Huang, Shi-Yu and Tsai, Kun-Han and Cheng, Wu-Tung}, biburl = {https://www.bibsonomy.org/bibtex/206734fb2d72e951cfa0916fba52dd89d/dblp}, ee = {https://doi.org/10.1109/TCAD.2018.2789779}, interhash = {ebb320819fa6dcc5d84299b789329a47}, intrahash = {06734fb2d72e951cfa0916fba52dd89d}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 10, pages = {2087-2097}, timestamp = {2020-09-25T11:46:28.000+0200}, title = {Circuit and Methodology for Testing Small Delay Faults in the Clock Network.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#YangWHTC18}, volume = 37, year = 2018 }