%0 Conference Paper %1 conf/glvlsi/GargSGJGK06 %A Garg, Rajesh %A Sánchez, Mario %A Gulati, Kanupriya %A Jayakumar, Nikhil %A Gupta, Anshul %A Khatri, Sunil P. %B ACM Great Lakes Symposium on VLSI %D 2006 %E Qu, Gang %E Ismail, Yehea I. %E Vijaykrishnan, Narayanan %E Zhou, Hai %I ACM %K dblp %P 217-222 %T A design flow to optimize circuit delay by using standard cells and PLAs. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2006.html#GargSGJGK06 %@ 1-59593-347-6

@inproceedings{conf/glvlsi/GargSGJGK06, added-at = {2022-10-20T00:00:00.000+0200}, author = {Garg, Rajesh and Sánchez, Mario and Gulati, Kanupriya and Jayakumar, Nikhil and Gupta, Anshul and Khatri, Sunil P.}, biburl = {https://www.bibsonomy.org/bibtex/25e24499c49a62b26c8fe522d9800785d/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2006}, editor = {Qu, Gang and Ismail, Yehea I. and Vijaykrishnan, Narayanan and Zhou, Hai}, ee = {https://doi.org/10.1145/1127908.1127960}, interhash = {ec7504a3ce0a306526db0dff19ef3df4}, intrahash = {5e24499c49a62b26c8fe522d9800785d}, isbn = {1-59593-347-6}, keywords = {dblp}, pages = {217-222}, publisher = {ACM}, timestamp = {2024-04-09T22:51:45.000+0200}, title = {A design flow to optimize circuit delay by using standard cells and PLAs.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2006.html#GargSGJGK06}, year = 2006 }