%0 Conference Paper %1 conf/mwscas/WilleD13 %A Wille, Robert %A Drechsler, Rolf %B MWSCAS %D 2013 %I IEEE %K dblp %P 1063-1066 %T The SyReC hardware description language: Enabling scalable synthesis of reversible circuits. %U http://dblp.uni-trier.de/db/conf/mwscas/mwscas2013.html#WilleD13

@inproceedings{conf/mwscas/WilleD13, added-at = {2020-06-15T00:00:00.000+0200}, author = {Wille, Robert and Drechsler, Rolf}, biburl = {https://www.bibsonomy.org/bibtex/21e365f0c9ce74cb83a8fa665dac5e404/dblp}, booktitle = {MWSCAS}, crossref = {conf/mwscas/2013}, ee = {https://www.wikidata.org/entity/Q59242400}, interhash = {ed39ca46e408aaf026230dc820ac4e60}, intrahash = {1e365f0c9ce74cb83a8fa665dac5e404}, keywords = {dblp}, pages = {1063-1066}, publisher = {IEEE}, timestamp = {2024-04-09T10:44:14.000+0200}, title = {The SyReC hardware description language: Enabling scalable synthesis of reversible circuits.}, url = {http://dblp.uni-trier.de/db/conf/mwscas/mwscas2013.html#WilleD13}, year = 2013 }