Inproceedings,
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
J. Yang, H. Ko, K. Kim, H. Park, J. Park, J. Kang, J. Cha, S. Kim, Y. Kim, M. Park, G. Lee, K. Lee, S. Lee, G. Jeon, S. Jeong, Y. Joo, J. Cha, S. Hwang, B. Kim, S. Byeon, S. Lee, H. Park, J. Cho, and J. Kim.ISSCC, page 232-234. IEEE, (2024)
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- BibTeX key
- conf/isscc/YangKKPPKCKKPLLLJJJCHKBLPCK24
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2024
- pages
- 232-234
- publisher
- IEEE
- crossref
- conf/isscc/2024
- ee
- https://doi.org/10.1109/ISSCC49657.2024.10454560
- isbn
- 979-8-3503-0620-0
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#YangKKPPKCKKPLLLJJJCHKBLPCK24
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- please select -%0 Conference Paper
%1 conf/isscc/YangKKPPKCKKPLLLJJJCHKBLPCK24
%A Yang, Jaehyeok
%A Ko, Hyeongjun
%A Kim, Kyunghoon
%A Park, Hyunsu
%A Park, Jihwan
%A Kang, Ji-Hyo
%A Cha, Jin-Youp
%A Kim, Seongjin
%A Kim, Youngtaek
%A Park, Minsoo
%A Lee, Gangsik
%A Lee, Keonho
%A Lee, Sanghoon
%A Jeon, Gyunam
%A Jeong, Sera
%A Joo, Yongsuk
%A Cha, Jaehoon
%A Hwang, Seonwoo
%A Kim, Boram
%A Byeon, Sang-Yeon
%A Lee, Sungkwon
%A Park, Hyeonyeol
%A Cho, Joohwan
%A Kim, Jonghwan
%B ISSCC
%D 2024
%I IEEE
%K dblp
%P 232-234
%T 13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#YangKKPPKCKKPLLLJJJCHKBLPCK24
%@ 979-8-3503-0620-0
@inproceedings{conf/isscc/YangKKPPKCKKPLLLJJJCHKBLPCK24,
added-at = {2024-03-19T00:00:00.000+0100},
author = {Yang, Jaehyeok and Ko, Hyeongjun and Kim, Kyunghoon and Park, Hyunsu and Park, Jihwan and Kang, Ji-Hyo and Cha, Jin-Youp and Kim, Seongjin and Kim, Youngtaek and Park, Minsoo and Lee, Gangsik and Lee, Keonho and Lee, Sanghoon and Jeon, Gyunam and Jeong, Sera and Joo, Yongsuk and Cha, Jaehoon and Hwang, Seonwoo and Kim, Boram and Byeon, Sang-Yeon and Lee, Sungkwon and Park, Hyeonyeol and Cho, Joohwan and Kim, Jonghwan},
biburl = {https://www.bibsonomy.org/bibtex/2ee5ed08a8c26fd8c54b95af6d2616fc4/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2024},
ee = {https://doi.org/10.1109/ISSCC49657.2024.10454560},
interhash = {ee49a613c29414434d52bbfabb5b24d3},
intrahash = {ee5ed08a8c26fd8c54b95af6d2616fc4},
isbn = {979-8-3503-0620-0},
keywords = {dblp},
pages = {232-234},
publisher = {IEEE},
timestamp = {2024-04-09T20:43:07.000+0200},
title = {13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#YangKKPPKCKKPLLLJJJCHKBLPCK24},
year = 2024
}