%0 Conference Paper %1 conf/vlsic/WangWWY18 %A Wang, Yu-Zhe %A Wang, Yao-Pin %A Wu, Yi-Chung %A Yang, Chia-Hsiang %B VLSI Circuits %D 2018 %I IEEE %K dblp %P 261-262 %T A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#WangWWY18 %@ 978-1-5386-4214-6

@inproceedings{conf/vlsic/WangWWY18, added-at = {2019-09-25T00:00:00.000+0200}, author = {Wang, Yu-Zhe and Wang, Yao-Pin and Wu, Yi-Chung and Yang, Chia-Hsiang}, biburl = {https://www.bibsonomy.org/bibtex/2c7e767cef33b8aa3361ddd70110521ab/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2018}, ee = {https://doi.org/10.1109/VLSIC.2018.8502321}, interhash = {f0206d623ceeca2346706466ea696389}, intrahash = {c7e767cef33b8aa3361ddd70110521ab}, isbn = {978-1-5386-4214-6}, keywords = {dblp}, pages = {261-262}, publisher = {IEEE}, timestamp = {2019-09-26T13:07:18.000+0200}, title = {A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#WangWWY18}, year = 2018 }