%0 Conference Paper %1 conf/fpga/LiXZPWL19 %A Li, Zhengjie %A Xiao, Yuanlong %A Zhang, Yufan %A Pang, Yunbing %A Wang, Jian %A Lai, Jinmei %B FPGA %D 2019 %E Bazargan, Kia %E Neuendorffer, Stephen %I ACM %K dblp %P 121 %T Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. %U http://dblp.uni-trier.de/db/conf/fpga/fpga2019.html#LiXZPWL19 %@ 978-1-4503-6137-8

@inproceedings{conf/fpga/LiXZPWL19, added-at = {2019-10-17T00:00:00.000+0200}, author = {Li, Zhengjie and Xiao, Yuanlong and Zhang, Yufan and Pang, Yunbing and Wang, Jian and Lai, Jinmei}, biburl = {https://www.bibsonomy.org/bibtex/2d784cf1bda343f885a54eb3c2c29c109/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2019}, editor = {Bazargan, Kia and Neuendorffer, Stephen}, ee = {https://doi.org/10.1145/3289602.3293955}, interhash = {f19284b5464610cb6880707585293f4a}, intrahash = {d784cf1bda343f885a54eb3c2c29c109}, isbn = {978-1-4503-6137-8}, keywords = {dblp}, pages = 121, publisher = {ACM}, timestamp = {2019-10-18T11:42:25.000+0200}, title = {Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2019.html#LiXZPWL19}, year = 2019 }