%0 Conference Paper %1 conf/glvlsi/ChenY13 %A Chen, Zhi-Wei %A Yan, Jin-Tai %B ACM Great Lakes Symposium on VLSI %D 2013 %E Ayala, José Luis %E Jones, Alex K. %E Madden, Patrick H. %E Coskun, Ayse K. %I ACM %K dblp %P 347-348 %T Timing-constrained replacement using spare cells for design changes. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2013.html#ChenY13 %@ 978-1-4503-2032-0

@inproceedings{conf/glvlsi/ChenY13, added-at = {2018-11-06T00:00:00.000+0100}, author = {Chen, Zhi-Wei and Yan, Jin-Tai}, biburl = {https://www.bibsonomy.org/bibtex/2e9c1aee9daf0a47afddd9ca19737c4d8/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2013}, editor = {Ayala, José Luis and Jones, Alex K. and Madden, Patrick H. and Coskun, Ayse K.}, ee = {https://doi.org/10.1145/2483028.2483136}, interhash = {f1933cc86aa1177147d6275f9bfdc0e3}, intrahash = {e9c1aee9daf0a47afddd9ca19737c4d8}, isbn = {978-1-4503-2032-0}, keywords = {dblp}, pages = {347-348}, publisher = {ACM}, timestamp = {2019-07-24T11:38:00.000+0200}, title = {Timing-constrained replacement using spare cells for design changes.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2013.html#ChenY13}, year = 2013 }