%0 Conference Paper %1 conf/cso/RenACXW09 %A Ren, Yongqing %A An, Hong %A Cong, Ming %A Xu, Guang %A Wang, Li %B CSO (1) %D 2009 %E Yu, Lean %E Lai, Kin Keung %E Mishra, Shashi Kant %I IEEE Computer Society %K dblp %P 77-81 %T Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology. %U http://dblp.uni-trier.de/db/conf/cso/cso2009-1.html#RenACXW09 %@ 978-0-7695-3605-7

@inproceedings{conf/cso/RenACXW09, added-at = {2023-03-23T00:00:00.000+0100}, author = {Ren, Yongqing and An, Hong and Cong, Ming and Xu, Guang and Wang, Li}, biburl = {https://www.bibsonomy.org/bibtex/293476d337787efe07f2580939846d41b/dblp}, booktitle = {CSO (1)}, crossref = {conf/cso/2009-1}, editor = {Yu, Lean and Lai, Kin Keung and Mishra, Shashi Kant}, ee = {https://doi.ieeecomputersociety.org/10.1109/CSO.2009.233}, interhash = {f203c441157b53a8aba4a4d8eabed941}, intrahash = {93476d337787efe07f2580939846d41b}, isbn = {978-0-7695-3605-7}, keywords = {dblp}, pages = {77-81}, publisher = {IEEE Computer Society}, timestamp = {2024-04-09T17:50:30.000+0200}, title = {Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology.}, url = {http://dblp.uni-trier.de/db/conf/cso/cso2009-1.html#RenACXW09}, year = 2009 }