%0 Conference Paper %1 conf/ismvl/ZhangWHK09 %A Zhang, Wancheng %A Wu, Nan-Jian %A Hashizume, Tamotsu %A Kasai, Seiya %B ISMVL %D 2009 %I IEEE Computer Society %K dblp %P 337-342 %T Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors. %U http://dblp.uni-trier.de/db/conf/ismvl/ismvl2009.html#ZhangWHK09 %@ 978-0-7695-3607-1

@inproceedings{conf/ismvl/ZhangWHK09, added-at = {2023-03-23T00:00:00.000+0100}, author = {Zhang, Wancheng and Wu, Nan-Jian and Hashizume, Tamotsu and Kasai, Seiya}, biburl = {https://www.bibsonomy.org/bibtex/265ff92b6b408648e066b7793874e00d5/dblp}, booktitle = {ISMVL}, crossref = {conf/ismvl/2009}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISMVL.2009.13}, interhash = {f31660763dbc89c4dc65e9a6f12bc96c}, intrahash = {65ff92b6b408648e066b7793874e00d5}, isbn = {978-0-7695-3607-1}, keywords = {dblp}, pages = {337-342}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T17:17:41.000+0200}, title = {Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors.}, url = {http://dblp.uni-trier.de/db/conf/ismvl/ismvl2009.html#ZhangWHK09}, year = 2009 }