%0 Journal Article %1 journals/ieiceee/XuWLCY23 %A Xu, Yantian %A Wang, Zhiyu %A Liu, Jiarui %A Chen, Hua %A Yu, Faxin %D 2023 %J IEICE Electron. Express %K dblp %N 9 %P 20230035 %T Multi-chip phase synchronization circuit of fractional-N PLL. %U http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee20.html#XuWLCY23 %V 20

@article{journals/ieiceee/XuWLCY23, added-at = {2024-07-26T00:00:00.000+0200}, author = {Xu, Yantian and Wang, Zhiyu and Liu, Jiarui and Chen, Hua and Yu, Faxin}, biburl = {https://www.bibsonomy.org/bibtex/29a895486fed8fc4b41cdc9bd9e57ce89/dblp}, ee = {https://doi.org/10.1587/elex.20.20230035}, interhash = {f755c9b20d9b0f491023059a61eee76f}, intrahash = {9a895486fed8fc4b41cdc9bd9e57ce89}, journal = {IEICE Electron. Express}, keywords = {dblp}, number = 9, pages = 20230035, timestamp = {2024-07-29T07:10:05.000+0200}, title = {Multi-chip phase synchronization circuit of fractional-N PLL.}, url = {http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee20.html#XuWLCY23}, volume = 20, year = 2023 }