%0 Conference Paper %1 conf/glvlsi/BubnaRSM08 %A Bubna, Mayur %A Roy, Sudip %A Shenoy, Naresh %A Mazumdar, Subhra %B ACM Great Lakes Symposium on VLSI %D 2008 %E Narayanan, Vijaykrishnan %E Yan, Zhiyuan %E Macii, Enrico %E Bhanja, Sanjukta %I ACM %K dblp %P 243-248 %T A layout-aware physical design method for constructing feasible QCA circuits. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2008.html#BubnaRSM08 %@ 978-1-59593-999-9

@inproceedings{conf/glvlsi/BubnaRSM08, added-at = {2018-11-06T00:00:00.000+0100}, author = {Bubna, Mayur and Roy, Sudip and Shenoy, Naresh and Mazumdar, Subhra}, biburl = {https://www.bibsonomy.org/bibtex/2372a8cd2177fe21c514309b84bc0ee03/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2008}, editor = {Narayanan, Vijaykrishnan and Yan, Zhiyuan and Macii, Enrico and Bhanja, Sanjukta}, ee = {https://doi.org/10.1145/1366110.1366170}, interhash = {f7c44e18b8664d9c9812db7462442a24}, intrahash = {372a8cd2177fe21c514309b84bc0ee03}, isbn = {978-1-59593-999-9}, keywords = {dblp}, pages = {243-248}, publisher = {ACM}, timestamp = {2018-11-07T14:25:13.000+0100}, title = {A layout-aware physical design method for constructing feasible QCA circuits.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2008.html#BubnaRSM08}, year = 2008 }