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%0 Conference Paper
%1 conf/icassp/Alexandropoulos20a
%A Alexandropoulos, George C.
%A Vlachos, Evangelos
%B ICASSP
%D 2020
%I IEEE
%K dblp
%P 9175-9179
%T A Hardware Architecture For Reconfigurable Intelligent Surfaces with Minimal Active Elements for Explicit Channel Estimation.
%U http://dblp.uni-trier.de/db/conf/icassp/icassp2020.html#Alexandropoulos20a
%@ 978-1-5090-6631-5
@inproceedings{conf/icassp/Alexandropoulos20a,
added-at = {2020-07-23T00:00:00.000+0200},
author = {Alexandropoulos, George C. and Vlachos, Evangelos},
biburl = {https://www.bibsonomy.org/bibtex/2baa35d640348384e040a96fc16a46e8b/dblp},
booktitle = {ICASSP},
crossref = {conf/icassp/2020},
ee = {https://doi.org/10.1109/ICASSP40776.2020.9053976},
interhash = {f888303b8f0c7f00c33149b7e1d9006b},
intrahash = {baa35d640348384e040a96fc16a46e8b},
isbn = {978-1-5090-6631-5},
keywords = {dblp},
pages = {9175-9179},
publisher = {IEEE},
timestamp = {2020-07-24T11:36:02.000+0200},
title = {A Hardware Architecture For Reconfigurable Intelligent Surfaces with Minimal Active Elements for Explicit Channel Estimation.},
url = {http://dblp.uni-trier.de/db/conf/icassp/icassp2020.html#Alexandropoulos20a},
year = 2020
}
