%0 Journal Article %1 journals/ieicet/WangLI06 %A Wang, Shuaiqi %A Li, Fule %A Inoue, Yasuaki %D 2006 %J IEICE Trans. Fundam. Electron. Commun. Comput. Sci. %K dblp %N 10 %P 2732-2739 %T A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet89a.html#WangLI06 %V 89-A

@article{journals/ieicet/WangLI06, added-at = {2020-04-11T00:00:00.000+0200}, author = {Wang, Shuaiqi and Li, Fule and Inoue, Yasuaki}, biburl = {https://www.bibsonomy.org/bibtex/28fa286f3949d162f23fcbbdf3415034c/dblp}, ee = {https://doi.org/10.1093/ietfec/e89-a.10.2732}, interhash = {f96556e2ced5e50fe3cd8fc4199b270e}, intrahash = {8fa286f3949d162f23fcbbdf3415034c}, journal = {IEICE Trans. Fundam. Electron. Commun. Comput. Sci.}, keywords = {dblp}, number = 10, pages = {2732-2739}, timestamp = {2020-04-14T12:03:07.000+0200}, title = {A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet89a.html#WangLI06}, volume = {89-A}, year = 2006 }