%0 Conference Paper %1 conf/vlsid/RaghunathanRL00 %A Raghunathan, Vijay %A Ravi, Srivaths %A Lakshminarayana, Ganesh %B VLSI Design %D 2000 %I IEEE Computer Society %K dblp %P 220-227 %T High-Level Synthesis with Variable-Latency Components. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#RaghunathanRL00 %@ 0-7695-0487-6

@inproceedings{conf/vlsid/RaghunathanRL00, added-at = {2023-03-24T00:00:00.000+0100}, author = {Raghunathan, Vijay and Ravi, Srivaths and Lakshminarayana, Ganesh}, biburl = {https://www.bibsonomy.org/bibtex/28e1f526e09a10901046d37e4fcb7da7a/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2000}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812612}, interhash = {fb29fd5ecd68789489ceb81f53918b74}, intrahash = {8e1f526e09a10901046d37e4fcb7da7a}, isbn = {0-7695-0487-6}, keywords = {dblp}, pages = {220-227}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:19:01.000+0200}, title = {High-Level Synthesis with Variable-Latency Components.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#RaghunathanRL00}, year = 2000 }