%0 Journal Article %1 journals/tcas/HwangJR09 %A Hwang, Myeong-Eun %A Jung, Seong-Ook %A Roy, Kaushik %D 2009 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 7 %P 1428-1441 %T Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI56.html#HwangJR09 %V 56-I

@article{journals/tcas/HwangJR09, added-at = {2020-05-22T00:00:00.000+0200}, author = {Hwang, Myeong-Eun and Jung, Seong-Ook and Roy, Kaushik}, biburl = {https://www.bibsonomy.org/bibtex/21fd8bdbdc3a9382f578ea99f5887ebdc/dblp}, ee = {https://doi.org/10.1109/TCSI.2008.2006217}, interhash = {e994b84d1be7f4747bbccb67f34536c4}, intrahash = {1fd8bdbdc3a9382f578ea99f5887ebdc}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 7, pages = {1428-1441}, timestamp = {2020-05-23T12:31:32.000+0200}, title = {Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI56.html#HwangJR09}, volume = {56-I}, year = 2009 }