We present room temperature memristive switching in a nano-patterned $LaAlO_3/SrTiO_3$ wire with laterally defined gates in proximity to the wire. Closed bias voltage sweeps show pinched hysteresis loops with zero bias resistance values of up to Ron = 8 MΩ and Roff = 1.2 GΩ for the on and off state, respectively. The maximum $R_off/Ron$ ratio is 150. Frequency dependent measurements show a cutoff frequency of around 10 Hz, and the alteration of set point voltages enables us to precisely set and control the resistance off-on ratio. We explain the memristive switching by charge localization on the laterally defined gates, which couple capacitively to the wire and enhance or decrease the resistance dependent on the amount of transferred charges. Our finding enables the realization of geometry-based memristive switching devices, which make use of the form-dependent wire-gate capacitance.
Description
Room temperature memristive switching in nano-patterned LaAlO3/SrTiO3 wires with laterally defined gates: Applied Physics Letters: Vol 118, No 15
%0 Journal Article
%1 noauthororeditor
%A Miller, K.
%A Hartmann, F.
%A Leikert, B.
%A Kuhn, S.
%A Gabel, J.
%A Sing, M.
%A Claessen, R.
%A Höfling, S.
%D 2021
%J Appl. Phys. Lett.
%K a d
%P 153502
%R https://doi.org/10.1063/5.0037416
%T Room temperature memristive switching in nano-patterned LaAlO$_3$/SrTiO$_3$ wires with laterally defined gates
%U https://aip.scitation.org/doi/abs/10.1063/5.0037416?journalCode=apl
%V 118
%X We present room temperature memristive switching in a nano-patterned $LaAlO_3/SrTiO_3$ wire with laterally defined gates in proximity to the wire. Closed bias voltage sweeps show pinched hysteresis loops with zero bias resistance values of up to Ron = 8 MΩ and Roff = 1.2 GΩ for the on and off state, respectively. The maximum $R_off/Ron$ ratio is 150. Frequency dependent measurements show a cutoff frequency of around 10 Hz, and the alteration of set point voltages enables us to precisely set and control the resistance off-on ratio. We explain the memristive switching by charge localization on the laterally defined gates, which couple capacitively to the wire and enhance or decrease the resistance dependent on the amount of transferred charges. Our finding enables the realization of geometry-based memristive switching devices, which make use of the form-dependent wire-gate capacitance.
@article{noauthororeditor,
abstract = {We present room temperature memristive switching in a nano-patterned $LaAlO_3/SrTiO_3$ wire with laterally defined gates in proximity to the wire. Closed bias voltage sweeps show pinched hysteresis loops with zero bias resistance values of up to Ron = 8 MΩ and Roff = 1.2 GΩ for the on and off state, respectively. The maximum $R_{off}/R{on}$ ratio is 150. Frequency dependent measurements show a cutoff frequency of around 10 Hz, and the alteration of set point voltages enables us to precisely set and control the resistance off-on ratio. We explain the memristive switching by charge localization on the laterally defined gates, which couple capacitively to the wire and enhance or decrease the resistance dependent on the amount of transferred charges. Our finding enables the realization of geometry-based memristive switching devices, which make use of the form-dependent wire-gate capacitance.},
added-at = {2021-05-12T11:44:27.000+0200},
author = {Miller, K. and Hartmann, F. and Leikert, B. and Kuhn, S. and Gabel, J. and Sing, M. and Claessen, R. and Höfling, S.},
biburl = {https://www.bibsonomy.org/bibtex/22b0f2e6337cfa4c9cb6fba7d11bb2937/ctqmat},
day = 14,
description = {Room temperature memristive switching in nano-patterned LaAlO3/SrTiO3 wires with laterally defined gates: Applied Physics Letters: Vol 118, No 15},
doi = {https://doi.org/10.1063/5.0037416},
interhash = {bb26ad4d620bff6715fabada3cd83ab5},
intrahash = {2b0f2e6337cfa4c9cb6fba7d11bb2937},
journal = {Appl. Phys. Lett.},
keywords = {a d},
month = {04},
pages = 153502,
timestamp = {2023-10-19T10:16:09.000+0200},
title = {Room temperature memristive switching in nano-patterned LaAlO$_{\mathbf{3}}$/SrTiO$_{\mathbf{3}}$ wires with laterally defined gates
},
url = {https://aip.scitation.org/doi/abs/10.1063/5.0037416?journalCode=apl},
volume = 118,
year = 2021
}