%0 Journal Article %1 journals/jssc/PelleranoPS08 %A Pellerano, Stefano %A Palaskas, Yorgos %A Soumyanath, Krishnamurthy %D 2008 %J IEEE J. Solid State Circuits %K dblp %N 7 %P 1542-1552 %T A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#PelleranoPS08 %V 43

@article{journals/jssc/PelleranoPS08, added-at = {2020-08-30T00:00:00.000+0200}, author = {Pellerano, Stefano and Palaskas, Yorgos and Soumyanath, Krishnamurthy}, biburl = {https://www.bibsonomy.org/bibtex/22b838ce39f7b8649afe997cd62d9d2b4/dblp}, ee = {https://doi.org/10.1109/JSSC.2008.922395}, interhash = {5c3d5f073d0fb6f44596bcea998e883f}, intrahash = {2b838ce39f7b8649afe997cd62d9d2b4}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 7, pages = {1542-1552}, timestamp = {2020-08-31T11:43:59.000+0200}, title = {A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#PelleranoPS08}, volume = 43, year = 2008 }