%0 Journal Article %1 5678607 %A Pham, Phi-Hung %A Park, Jongsun %A Mau, Phuong %A Kim, Chulwoo %D 2012 %J Very Large Scale Integration (VLSI) Systems, IEEE Transactions on %K backtracking noc pipeline wave %N 2 %P 270-283 %R 10.1109/TVLSI.2010.2096520 %T Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip %U http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5678607 %V 20 %X It is a challenging task in a network-on-chip to design an on-chip switch/router to dynamically support (hard) guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. This paper presents the design and implementation of a novel pipeline circuit-switched switch to support guaranteed throughput. The proposed circuit-switched switch, based on a backtracking probing path setup, operates with a source-synchronous wave-pipeline approach. The switch can support a dead- and live-lock free dynamic path-setup scheme and can achieve high bandwidth and high area and energy efficiency. A silicon-proven prototype of a 16-bit-data 5-bidirectional-port switch in a four-metal-layer 0.18-μ m CMOS standard-cell technology can yield an aggregate data bandwidth of up to 73.84 Gb/s, while occupying only a modest area of 0.0315 mm². The synthesizable implementation of the proposed switch also results in a cost-effective design, fast development time, and portability.

@article{5678607, abstract = {It is a challenging task in a network-on-chip to design an on-chip switch/router to dynamically support (hard) guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. This paper presents the design and implementation of a novel pipeline circuit-switched switch to support guaranteed throughput. The proposed circuit-switched switch, based on a backtracking probing path setup, operates with a source-synchronous wave-pipeline approach. The switch can support a dead- and live-lock free dynamic path-setup scheme and can achieve high bandwidth and high area and energy efficiency. A silicon-proven prototype of a 16-bit-data 5-bidirectional-port switch in a four-metal-layer 0.18-μ m CMOS standard-cell technology can yield an aggregate data bandwidth of up to 73.84 Gb/s, while occupying only a modest area of 0.0315 mm². The synthesizable implementation of the proposed switch also results in a cost-effective design, fast development time, and portability.}, added-at = {2013-04-04T16:07:13.000+0200}, author = {Pham, Phi-Hung and Park, Jongsun and Mau, Phuong and Kim, Chulwoo}, biburl = {https://www.bibsonomy.org/bibtex/239bf21e12246c4b7575bd5e9d06ea62f/eberle18}, description = {IEEE Xplore - Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in N...}, doi = {10.1109/TVLSI.2010.2096520}, interhash = {db59a1bb2761d368d3985b766c295fb6}, intrahash = {39bf21e12246c4b7575bd5e9d06ea62f}, issn = {1063-8210}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, keywords = {backtracking noc pipeline wave}, number = 2, pages = {270-283}, timestamp = {2013-04-04T16:07:13.000+0200}, title = {Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5678607}, volume = 20, year = 2012 }