%0 Conference Paper %1 chandra2005predicting %A Chandra, D. %A Guo, F. %A Kim, S. %A Solihin, Y. %B High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on %D 2005 %K cache cmp multiprocessor %P 340--351 %R 10.1109/HPCA.2005.27 %T Predicting inter-thread cache contention on a chip multi-processor architecture

@inproceedings{chandra2005predicting, added-at = {2012-09-21T22:32:52.000+0200}, author = {Chandra, D. and Guo, F. and Kim, S. and Solihin, Y.}, biburl = {https://www.bibsonomy.org/bibtex/249820062b20d87fc2e658562fbb1c4ae/ytyoun}, booktitle = {High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on}, doi = {10.1109/HPCA.2005.27}, interhash = {77e2bb32506b388cdcd1b2985fbbcdc0}, intrahash = {49820062b20d87fc2e658562fbb1c4ae}, keywords = {cache cmp multiprocessor}, organization = {IEEE}, pages = {340--351}, timestamp = {2012-09-21T22:32:52.000+0200}, title = {Predicting inter-thread cache contention on a chip multi-processor architecture}, year = 2005 }