Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning
C. Vogel, D. Draxelmayr, and F. Kuttner. The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04., 1, page 341--344. (July 2004)
Abstract
We analyze transfer characteristic mismatches of sample-and-hold circuits in time-interleaved analog-to-digital converters and show their intrinsic connection to aperture delay mismatches. Both cause linear-phase mismatches, i.e., timing mismatches, which significantly degrade the signal-to-noise ratio. Based on our analysis, we introduce a novel power-saving method to correct timing mismatches among the channels by tuning the transfer characteristics of the sample-and-holds. Simulation results confirm the prospects of the presented method.
%0 Conference Paper
%1 Vogel2004Compensation
%A Vogel, Christian
%A Draxelmayr, Dieter
%A Kuttner, Franz
%B The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.
%D 2004
%K adc, compensation, interleaved, mismatches, time, timing
%P 341--344
%T Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning
%U http://dx.doi.org/10.1109/MWSCAS.2004.1353997
%V 1
%X We analyze transfer characteristic mismatches of sample-and-hold circuits in time-interleaved analog-to-digital converters and show their intrinsic connection to aperture delay mismatches. Both cause linear-phase mismatches, i.e., timing mismatches, which significantly degrade the signal-to-noise ratio. Based on our analysis, we introduce a novel power-saving method to correct timing mismatches among the channels by tuning the transfer characteristics of the sample-and-holds. Simulation results confirm the prospects of the presented method.
@inproceedings{Vogel2004Compensation,
abstract = {We analyze transfer characteristic mismatches of sample-and-hold circuits in time-interleaved analog-to-digital converters and show their intrinsic connection to aperture delay mismatches. Both cause linear-phase mismatches, i.e., timing mismatches, which significantly degrade the signal-to-noise ratio. Based on our analysis, we introduce a novel power-saving method to correct timing mismatches among the channels by tuning the transfer characteristics of the sample-and-holds. Simulation results confirm the prospects of the presented method.},
added-at = {2009-02-06T12:13:23.000+0100},
author = {Vogel, Christian and Draxelmayr, Dieter and Kuttner, Franz},
biburl = {https://www.bibsonomy.org/bibtex/272463f54ffcee8d672dcdd8ebbc1bd0d/peteru},
booktitle = {The 2004 47th Midwest Symposium on Circuits and Systems, 2004. {MWSCAS} '04. },
interhash = {f543cf60959e7ac74783eb8bdb77a17e},
intrahash = {72463f54ffcee8d672dcdd8ebbc1bd0d},
keywords = {adc, compensation, interleaved, mismatches, time, timing},
month = {July},
pages = {341--344},
timestamp = {2009-02-06T12:13:23.000+0100},
title = {Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning},
url = {http://dx.doi.org/10.1109/MWSCAS.2004.1353997},
volume = 1,
year = 2004
}