Most system-on-Chip (SoC) design methodologies promote the reuse of pre-designed (hardware, software, and functional) components. However, as these components are heterogeneous, their integration requires complex interface sub-systems. These sub-systems can also be constructed by assembling pre-designed basic interface components. Hence, SoC design and validation involves component composition techniques to create hardware, software, and functional interface sub-systems by assembling basic interface components. We propose a unified methodology for automatic component integration that allows designers to reuse pre-designed components effectively. We also present ROSES, a design flow that uses this methodology to generate hardware, software, and functional interface sub-systems automatically starting from a system-level architectural model.
%0 Conference Paper
%1 dziri2004unified
%A Dziri, M.
%A Cesário, W.
%A Jerraya, A.
%A Wagner, F.
%B Design Automation Conference
%D 2004
%K Architecture DATE Modelling
%T Unified Component Integration Flow for Multi-Processor SoC Design and Validation
%U http://date.eda-online.co.uk/proceedings/papers/2004/date04/pdffiles/09a_1.pdf
%X Most system-on-Chip (SoC) design methodologies promote the reuse of pre-designed (hardware, software, and functional) components. However, as these components are heterogeneous, their integration requires complex interface sub-systems. These sub-systems can also be constructed by assembling pre-designed basic interface components. Hence, SoC design and validation involves component composition techniques to create hardware, software, and functional interface sub-systems by assembling basic interface components. We propose a unified methodology for automatic component integration that allows designers to reuse pre-designed components effectively. We also present ROSES, a design flow that uses this methodology to generate hardware, software, and functional interface sub-systems automatically starting from a system-level architectural model.
@inproceedings{dziri2004unified,
abstract = {Most system-on-Chip (SoC) design methodologies promote the reuse of pre-designed (hardware, software, and functional) components. However, as these components are heterogeneous, their integration requires complex interface sub-systems. These sub-systems can also be constructed by assembling pre-designed basic interface components. Hence, SoC design and validation involves component composition techniques to create hardware, software, and functional interface sub-systems by assembling basic interface components. We propose a unified methodology for automatic component integration that allows designers to reuse pre-designed components effectively. We also present ROSES, a design flow that uses this methodology to generate hardware, software, and functional interface sub-systems automatically starting from a system-level architectural model.},
added-at = {2007-04-12T13:21:42.000+0200},
author = {Dziri, M. and Ces{\'a}rio, W. and Jerraya, A. and Wagner, F.},
biburl = {https://www.bibsonomy.org/bibtex/276607d50e41dfcba8eeda4e20e16b337/derkling},
booktitle = {Design Automation Conference},
interhash = {a9f4d7cb0fcadcc4171925492186a8b4},
intrahash = {76607d50e41dfcba8eeda4e20e16b337},
keywords = {Architecture DATE Modelling},
local = {./AllPapers/2004_DATE_dziri2004unified.pdf},
timestamp = {2007-04-12T13:21:42.000+0200},
title = {Unified Component Integration Flow for Multi-Processor SoC Design and Validation},
url = {http://date.eda-online.co.uk/proceedings/papers/2004/date04/pdffiles/09a_1.pdf},
year = 2004
}