%0 Conference Paper %1 osgooi2012modeling %A Osgooi, M.N. %A Jahanian, A. %A Zarandi, H.-R. %B Computer Architecture and Digital Systems (CADS), 2012 16th CSI International Symposium on %D 2012 %K fpga seu %P 31-36 %R 10.1109/CADS.2012.6316415 %T Modeling, evaluation and mitigation of SEU error in three-dimensional FPGAs %U http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6316415&navigation=1 %X SEU error which is made by various radiations affects the signal integrity of nano-scale circuits, especially for future ultra-large and complex circuits. In this paper, we proposed a SEU error model for three-dimensional FPGAs and evaluate the SEU error of 3D-FPGAs based on the proposed model and then compare the SEU error rate of 3D-FPGAs with 2D-FPGAs. Moreover, we proposed a 3D layer assignment for improving SEU error possibility on three-dimensional FPGAs. The experimental results show that SEU error rate and critical delay decreases about 67% and 13.1% on 4 layers 3D-FPGA compared with 2D-FPGAs, respectively. In addition, the proposed layer assignment improves the possibility of SEU error of 3D-FPGAs up to 6.5% for large FPGA circuits.

@inproceedings{osgooi2012modeling, abstract = {SEU error which is made by various radiations affects the signal integrity of nano-scale circuits, especially for future ultra-large and complex circuits. In this paper, we proposed a SEU error model for three-dimensional FPGAs and evaluate the SEU error of 3D-FPGAs based on the proposed model and then compare the SEU error rate of 3D-FPGAs with 2D-FPGAs. Moreover, we proposed a 3D layer assignment for improving SEU error possibility on three-dimensional FPGAs. The experimental results show that SEU error rate and critical delay decreases about 67% and 13.1% on 4 layers 3D-FPGA compared with 2D-FPGAs, respectively. In addition, the proposed layer assignment improves the possibility of SEU error of 3D-FPGAs up to 6.5% for large FPGA circuits.}, added-at = {2014-10-15T13:34:08.000+0200}, author = {Osgooi, M.N. and Jahanian, A. and Zarandi, H.-R.}, biburl = {https://www.bibsonomy.org/bibtex/278867e33b4f26e487e0babbffc2ee753/eberle18}, booktitle = {Computer Architecture and Digital Systems (CADS), 2012 16th CSI International Symposium on}, description = {IEEE Xplore Abstract - Modeling, evaluation and mitigation of SEU error in three-dimensional FPGAs}, doi = {10.1109/CADS.2012.6316415}, interhash = {51ec32649f4347d6b73d9a0fc1f4a526}, intrahash = {78867e33b4f26e487e0babbffc2ee753}, keywords = {fpga seu}, month = may, pages = {31-36}, timestamp = {2014-10-15T13:34:08.000+0200}, title = {Modeling, evaluation and mitigation of SEU error in three-dimensional FPGAs}, url = {http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6316415&navigation=1}, year = 2012 }