A Novel Architecture Design & Characterization of CAM Controller IP Core with Replacement Policy
D. Hope (Hrsg.) Int. J. on Recent Trends in Engineering and Technology,, 8 (2):
5(Januar 2013)
Zusammenfassung
Content Addressable Memory (CAM) is a special
purpose Random Access Memory device that can be accessed
by searching for data content. This paper describes a novel
architecture design and characterization of a reusable soft IP
core for CAM controller with sequential replacement policy,
so as to improve the match ratio of the CAM memory. The
proposed design was modeled using Verilog HDL and also
prototyped in Xilinx® SPARTAN family FPGA.The power
analysis was done using XPower® analyzer and the hardware
test result was obtained by ChipScope® Pro logic analyzer.
%0 Journal Article
%1 hope2013novel
%D 2013
%E Hope, Dr.Martin
%J Int. J. on Recent Trends in Engineering and Technology,
%K Addressable Content Core IP Memory
%N 2
%P 5
%T A Novel Architecture Design & Characterization of CAM Controller IP Core with Replacement Policy
%U http://searchdl.org/public/journals/2013/IJRTET/8/2/28.pdf
%V 8
%X Content Addressable Memory (CAM) is a special
purpose Random Access Memory device that can be accessed
by searching for data content. This paper describes a novel
architecture design and characterization of a reusable soft IP
core for CAM controller with sequential replacement policy,
so as to improve the match ratio of the CAM memory. The
proposed design was modeled using Verilog HDL and also
prototyped in Xilinx® SPARTAN family FPGA.The power
analysis was done using XPower® analyzer and the hardware
test result was obtained by ChipScope® Pro logic analyzer.
@article{hope2013novel,
abstract = {Content Addressable Memory (CAM) is a special
purpose Random Access Memory device that can be accessed
by searching for data content. This paper describes a novel
architecture design and characterization of a reusable soft IP
core for CAM controller with sequential replacement policy,
so as to improve the match ratio of the CAM memory. The
proposed design was modeled using Verilog HDL and also
prototyped in Xilinx® SPARTAN family FPGA.The power
analysis was done using XPower® analyzer and the hardware
test result was obtained by ChipScope® Pro logic analyzer.},
added-at = {2014-02-03T07:46:11.000+0100},
biburl = {https://www.bibsonomy.org/bibtex/289a343c0d9dadec1514c19e61d625200/idescitation},
editor = {Hope, Dr.Martin},
interhash = {47adcd362273a6e0e2b406bb55c53186},
intrahash = {89a343c0d9dadec1514c19e61d625200},
journal = {Int. J. on Recent Trends in Engineering and Technology,},
keywords = {Addressable Content Core IP Memory},
month = {January},
number = 2,
pages = 5,
timestamp = {2014-02-03T07:46:11.000+0100},
title = {A Novel Architecture Design & Characterization of CAM Controller IP Core with Replacement Policy},
url = {http://searchdl.org/public/journals/2013/IJRTET/8/2/28.pdf},
volume = 8,
year = 2013
}