In VLSI Technology, flip-flops contribute a significant portion of chip area and power consumption to overall system design. Pulse triggered flip-flops (P-FF) have single latch and hence simpler in circuit complexity. Use of Explicit type design for P-FF gives the speed advantage. This paper presents various Pulse triggered Flip-flop (P-FF) designs and various techniques to achieve a better design in terms of power consumption and speed. Introduction of simple pass transistor in latch design can be used to speed up data transition. Dual edge triggering can be adopted as it consumes less power as compared to single edge triggering. Also conditional discharge technique can be used to reduce switching activity. The work is done in tanner tool software
%0 Journal Article
%1 Kshama_2015
%A Nikhade, Ms. Kshama N.
%A Khandait, Prof. A. P.
%D 2015
%I Auricle Technologies, Pvt., Ltd.
%J International Journal on Recent and Innovation Trends in Computing and Communication
%K Dual Edge Flip-Flop Pulse Triggered
%N 2
%P 672--675
%R 10.17762/ijritcc2321-8169.150251
%T A Novel Approach For Design Of Pulse Triggered Flip-Flop To Enhance Speed And Power
%U http://dx.doi.org/10.17762/ijritcc2321-8169.150251
%V 3
%X In VLSI Technology, flip-flops contribute a significant portion of chip area and power consumption to overall system design. Pulse triggered flip-flops (P-FF) have single latch and hence simpler in circuit complexity. Use of Explicit type design for P-FF gives the speed advantage. This paper presents various Pulse triggered Flip-flop (P-FF) designs and various techniques to achieve a better design in terms of power consumption and speed. Introduction of simple pass transistor in latch design can be used to speed up data transition. Dual edge triggering can be adopted as it consumes less power as compared to single edge triggering. Also conditional discharge technique can be used to reduce switching activity. The work is done in tanner tool software
@article{Kshama_2015,
abstract = {In VLSI Technology, flip-flops contribute a significant portion of chip area and power consumption to overall system design. Pulse triggered flip-flops (P-FF) have single latch and hence simpler in circuit complexity. Use of Explicit type design for P-FF gives the speed advantage. This paper presents various Pulse triggered Flip-flop (P-FF) designs and various techniques to achieve a better design in terms of power consumption and speed. Introduction of simple pass transistor in latch design can be used to speed up data transition. Dual edge triggering can be adopted as it consumes less power as compared to single edge triggering. Also conditional discharge technique can be used to reduce switching activity. The work is done in tanner tool software},
added-at = {2015-08-04T07:58:33.000+0200},
author = {Nikhade, Ms. Kshama N. and Khandait, Prof. A. P.},
biburl = {https://www.bibsonomy.org/bibtex/2bf7da851c5eccd5f2563538c2f1c1972/ijritcc},
doi = {10.17762/ijritcc2321-8169.150251},
interhash = {436193ee40476392e9e56e463e178b11},
intrahash = {bf7da851c5eccd5f2563538c2f1c1972},
journal = {International Journal on Recent and Innovation Trends in Computing and Communication},
keywords = {Dual Edge Flip-Flop Pulse Triggered},
month = {february},
number = 2,
pages = {672--675},
publisher = {Auricle Technologies, Pvt., Ltd.},
timestamp = {2015-08-04T07:58:33.000+0200},
title = {A Novel Approach For Design Of Pulse Triggered Flip-Flop To Enhance Speed And Power},
url = {http://dx.doi.org/10.17762/ijritcc2321-8169.150251},
volume = 3,
year = 2015
}