%0 Conference Paper %1 conf/nvmts/Ma15 %A Ma, Yanjun %B NVMTS %D 2015 %I IEEE %K dblp %P 1-3 %T Nonvolatile multibit SRAM, bit level caching, and multi-context computing for IoT. %U http://dblp.uni-trier.de/db/conf/nvmts/nvmts2015.html#Ma15 %@ 978-1-5090-2126-0

@inproceedings{conf/nvmts/Ma15, added-at = {2019-02-12T00:00:00.000+0100}, author = {Ma, Yanjun}, biburl = {https://www.bibsonomy.org/bibtex/2734be5310aac282b1a5b01997c84f67b/dblp}, booktitle = {NVMTS}, crossref = {conf/nvmts/2015}, ee = {https://doi.org/10.1109/NVMTS.2015.7457480}, interhash = {2c0a9baca05506078cd0a2aacecd2409}, intrahash = {734be5310aac282b1a5b01997c84f67b}, isbn = {978-1-5090-2126-0}, keywords = {dblp}, pages = {1-3}, publisher = {IEEE}, timestamp = {2020-02-18T11:47:46.000+0100}, title = {Nonvolatile multibit SRAM, bit level caching, and multi-context computing for IoT.}, url = {http://dblp.uni-trier.de/db/conf/nvmts/nvmts2015.html#Ma15}, year = 2015 }