%0 Conference Paper %1 conf/itc/ParulkarZPDM02 %A Parulkar, Ishwar %A Ziaja, Thomas A. %A Pendurkar, Rajesh %A D'Souza, Anand %A Majumdar, Amitava %B ITC %D 2002 %I IEEE Computer Society %K dblp %P 726-735 %T A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. %U http://dblp.uni-trier.de/db/conf/itc/itc2002.html#ParulkarZPDM02 %@ 0-7803-7543-2

@inproceedings{conf/itc/ParulkarZPDM02, added-at = {2024-04-18T00:00:00.000+0200}, author = {Parulkar, Ishwar and Ziaja, Thomas A. and Pendurkar, Rajesh and D'Souza, Anand and Majumdar, Amitava}, biburl = {https://www.bibsonomy.org/bibtex/2c406be0eb932c90620325d74215d693f/dblp}, booktitle = {ITC}, crossref = {conf/itc/2002}, ee = {https://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041825}, interhash = {c59c09f51d068ef1a7d2f6e39d209b5e}, intrahash = {c406be0eb932c90620325d74215d693f}, isbn = {0-7803-7543-2}, keywords = {dblp}, pages = {726-735}, publisher = {IEEE Computer Society}, timestamp = {2024-04-22T07:43:04.000+0200}, title = {A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors.}, url = {http://dblp.uni-trier.de/db/conf/itc/itc2002.html#ParulkarZPDM02}, year = 2002 }