@dblp

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control.

, , , , , , , , , , , , and . SoCC, page 110-115. IEEE, (2013)

Links and resources

Tags