%0 Journal Article %1 journals/vlsi/KangHS96 %A Kang, Sungho %A Hur, Youngmin %A Szygenda, Stephen A. %D 1996 %J VLSI Design %K dblp %N 2 %P 119-133 %T A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi4.html#KangHS96 %V 4

@article{journals/vlsi/KangHS96, added-at = {2024-07-15T00:00:00.000+0200}, author = {Kang, Sungho and Hur, Youngmin and Szygenda, Stephen A.}, biburl = {https://www.bibsonomy.org/bibtex/2d688b72fed3796bfda13eb175868c8b4/dblp}, ee = {https://doi.org/10.1155/1996/60318}, interhash = {631c4d6b64811ec681751121bdee0c89}, intrahash = {d688b72fed3796bfda13eb175868c8b4}, journal = {VLSI Design}, keywords = {dblp}, number = 2, pages = {119-133}, timestamp = {2024-07-22T07:03:55.000+0200}, title = {A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi4.html#KangHS96}, volume = 4, year = 1996 }