INTERCONNECT OPTIMIZATION FOR RELIABILITY
AND SCALABILITY
Advances in Interconnect Technologies: An International Journal(AITIJ), 01 (01):
13-19 (2018)Abstract
As process nodes continue to shrink to improve transistor density and performance, it is causing an
increase in resistance of interconnects. At higher voltages devices speed up even more, causing
interconnect to become the frequency limiter. Relatively in every node the interconnect delays continue to
increase. In High Speed designs timing optimization is done across several modes to coverage design for
multiple PVT points. With growing demand for Internet of Things (IoT) and autonomous driving, the need
for high speed designs to be reliable and dependable at extreme conditions of high voltage and temperature
continues to increase. Due to this the path profile across multiple PVT have changed with special focus on
high voltage due to interconnect dominance. While most tools are capable of multi corner optimization,
the increase in number of modes has challenges and more enhancements are needed to address
interconnect. One such area is Interconnect scaling with repeater optimization at Section and Full chip
levels. While previous papers have looked at several techniques to improve timing and slope for a given
corner 1, 2, 3, this paper describes a formula to design the repeater solution to optimize delay scaling
across different corners such as High Voltage and Typical Voltage to maximize performance.
Description
As process nodes continue to shrink to improve transistor density and performance, it is causing an
increase in resistance of interconnects. At higher voltages devices speed up even more, causing
interconnect to become the frequency limiter. Relatively in every node the interconnect delays continue to
increase. In High Speed designs timing optimization is done across several modes to coverage design for
multiple PVT points. With growing demand for Internet of Things (IoT) and autonomous driving, the need
for high speed designs to be reliable and dependable at extreme conditions of high voltage and temperature
continues to increase. Due to this the path profile across multiple PVT have changed with special focus on
high voltage due to interconnect dominance. While most tools are capable of multi corner optimization,
the increase in number of modes has challenges and more enhancements are needed to address
interconnect. One such area is Interconnect scaling with repeater optimization at Section and Full chip
levels. While previous papers have looked at several techniques to improve timing and slope for a given
corner [1], [2], [3], this paper describes a formula to design the repeater solution to optimize delay scaling
across different corners such as High Voltage and Typical Voltage to maximize performance.