%0 Journal Article %1 DavXie18Celerity %A Davidson, Scott %A Xie, Shaolin %A Torng, Christopher %A Al-Hawai, Khalid %A Rovinski, Austin %A Ajayi, Tutu %A Vega, Luis %A Zhao, Chun %A Zhao, Ritchie %A Dai, Steve %A others, %D 2018 %I IEEE %J IEEE Micro %K BNN Hardware RISC SoC accelerator architecture %N 2 %P 30--41 %T The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips %U https://ieeexplore.ieee.org/abstract/document/8344478 %V 38

@article{DavXie18Celerity, added-at = {2018-12-11T10:01:49.000+0100}, author = {Davidson, Scott and Xie, Shaolin and Torng, Christopher and Al-Hawai, Khalid and Rovinski, Austin and Ajayi, Tutu and Vega, Luis and Zhao, Chun and Zhao, Ritchie and Dai, Steve and others}, biburl = {https://www.bibsonomy.org/bibtex/2f21ddf5f94e3a431b0d386e63bc39160/loroch}, interhash = {f4dd32611d27b72c69f1d272e68e66e8}, intrahash = {f21ddf5f94e3a431b0d386e63bc39160}, journal = {IEEE Micro}, keywords = {BNN Hardware RISC SoC accelerator architecture}, number = 2, pages = {30--41}, publisher = {IEEE}, timestamp = {2018-12-11T10:01:49.000+0100}, title = {The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips}, url = {https://ieeexplore.ieee.org/abstract/document/8344478}, volume = 38, year = 2018 }