%0 Journal Article %1 noauthororeditor %A AL-Othman, AL-Mamoon %D 2017 %J International Journal of Computer Science, Engineering and Applications (IJCSEA) %K complementar gate pass to transis transmission %N 6 %P 1-10 %T THE INFLUENCE OF SILICON AREA ON THE PERFORMANCE OF THE FULL ADDERS %U http://aircconline.com/ijcsea/V7N6/7617ijcsea01.pdf %V 7 %X Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as 10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder implementation and, as a result, the delay time and power dissipation are significantly decreased. In order, to show the influence of the silicon area and transistors count on the performance of the 10-T full adder, it is compared to the most recent full adders : 28-T , 20T , 16-T , and 14 –T. Simulation result based on HSPICE simulator using 16nm technology showed that the 10-T XNOR full adder significantly improved the performance of full adder through decreasing the transistors count. In addition using the multi-supply voltage of 130nm technology, in this case the proposed full adder demonstrated is the best power consumption in comparison to other designs.

@article{noauthororeditor, abstract = {Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as 10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder implementation and, as a result, the delay time and power dissipation are significantly decreased. In order, to show the influence of the silicon area and transistors count on the performance of the 10-T full adder, it is compared to the most recent full adders : 28-T , 20T , 16-T , and 14 –T. Simulation result based on HSPICE simulator using 16nm technology showed that the 10-T XNOR full adder significantly improved the performance of full adder through decreasing the transistors count. In addition using the multi-supply voltage of 130nm technology, in this case the proposed full adder demonstrated is the best power consumption in comparison to other designs. }, added-at = {2018-01-12T05:22:46.000+0100}, author = {AL-Othman, AL-Mamoon}, biburl = {https://www.bibsonomy.org/bibtex/2b138e921abad3d5de1938b653ee6abd4/ijcsea}, interhash = {33c4e8e5ebfb4cd06e9e4fa496593cea}, intrahash = {b138e921abad3d5de1938b653ee6abd4}, journal = {International Journal of Computer Science, Engineering and Applications (IJCSEA)}, keywords = {complementar gate pass to transis transmission}, month = {December}, number = 6, pages = {1-10}, timestamp = {2018-01-12T05:22:46.000+0100}, title = {THE INFLUENCE OF SILICON AREA ON THE PERFORMANCE OF THE FULL ADDERS }, url = {http://aircconline.com/ijcsea/V7N6/7617ijcsea01.pdf}, volume = 7, year = 2017 }